1. Field of the Invention
The present invention relates to a fault self-supervising system of a cell processor in the ATM network. Particularly, the present invention relates to a fault self-supervising system which can supervise a fault, without interruption of normal operation of a communication apparatus, of an internal circuit formed of digital logical circuits such as an algorithm circuit, etc. in a cell processor such as a cell rate supervising apparatus, a cell switch and a traffic shaper.
2. Description of the Related Art
A cell processor having a fault supervising function of the related art is shown in FIG. 10. This apparatus is provided, within the cell processor such as the cell rate supervising apparatus, cell switch and traffic shaper, with a supervising cell application section 5 in the front stage of an arithmetic circuit 8 as the supervising object and a supervising cell termination section 10 at the rear stage thereof and moreover it is also provided with a supervising result expected value generating section 9 which generates an expected value of supervising result, a supervising cell generating section 4 and a cell pattern comparison/collation section 11.
In the fault supervising operation of this apparatus, the supervising result expected value generation section 9 recognizes first the normal operation of the arithmetic circuit 8 and generates a data as the supervising result expected value depending on the data inputted to the arithmetic circuit 8. On the basis of this supervising result expected value, the supervising cell generating section 4 generates a supervising cell. The supervising cell application section 5 detects a cell for supervising cell insertion such as an idle cell or a control cell, such as an OAM (Operation and Maintenance) cell and RM (Resource Management) cell, included in the flow of main signal cell or a particular cell inserted in the flow of cell for inserting the supervising cell. Moreover, the supervising cell application section 5 writes data in the supervising cell pattern over the detected cell as insertion of supervising cell. The arithmetic circuit 8 as the supervising object executes the processing of cell regardless of the supervising cell or the ordinary cell, and outputs the main signal cell flow including the supervising cell. The supervising cell termination section 10 extracts the supervising cell from the main signal cell flow output from the arithmetic circuit 8 and outputs it to the cell pattern comparison/collation section 11. Moreover, the supervising cell termination section 10 restores the cell pattern of the supervising cell to the cell pattern appearing before overwritten in the supervising cell application section 5 and outputs it to the main signal cell flow. The cell pattern comparison and collation section 11 can check whether the arithmetic circuits within the cell processor operates normally or not by comparing and collating the supervising cell extracted by the supervising cell termination section 10 with the supervising result expected value generated by the supervising result expected value generation section 9. In this case, the supervising cell is formed by a pseudo random data is added as the supervising data to the information field. The cell pattern comparison and collation section 11 collates the information field of this supervising cell with the information field of the supervising result expected value received from the supervising result expected value generation section 9.
The fault supervising system of the related art shown in FIG. 10 is capable of detecting a fault of digital logical circuits in the arithmetic circuits 8 in such a case that a supervising information, generated by the arithmetic circuit 8, indicating whether the arithmetic circuits 8 as the supervising object is operating normally or not is included in the cell header or information field of the supervising cell. However, in the case of a cell processor which controls an output interval of cell like an example of the traffic shaping, in place of the case where the supervising information indicating the operating condition of the arithmetic circuit 8 is written in direct in the cell header or information field of the supervising cell, a fault in the arithmetic circuit 8 cannot be detected. Namely, a fault where the arithmetic circuit 8 does not transmit the cells in the normal output interval cannot be detected with the technology of related art to judge coincidence of collation between the supervising data after the processing and the expected value.
Moreover, when the cell processor is composed of a plurality of arithmetic circuits and the supervising information in the supervising cell is uniquely determined depending on the operating condition of one arithmetic circuit within the cell processor, a defective arithmetic circuit can be identified through collation of the supervising information, but if the supervising information in the supervising cell is determined depending on the operating condition of a plurality of arithmetic circuits in the cell processor, it has been difficult to identify the defective arithmetic circuits among a plurality of circuits. Namely, when a plurality of arithmetic circuits execute the branching processing depending on the contents of the supervising information in the supervising cell, even if mismatching between the supervising data of the processing result and the expected value is detected by collation, fault location has been impossible for a plurality of arithmetic circuits.